CmdMaCC Project Status (04/24/2018 - 17:04:27) | |||
Project File: | CmdMCC.xise | Parser Errors: | No Errors |
Module Name: | CmdM3 | Implementation State: | Programming File Generated |
Target Device: | xc3s50an-5tqg144 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slices containing only related logic | 0 | 0 | 0% | ||
Number of Slices containing unrelated logic | 0 | 0 | 0% | ||
Number of bonded IOBs | 3 | 108 | 2% | ||
IOB Flip Flops | 1 | ||||
Number of BUFGMUXs | 1 | 24 | 4% | ||
Average Fanout of Non-Clock Nets | 1.00 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | lun. 23. avr. 07:38:16 2018 | ||||
Translation Report | Current | lun. 23. avr. 07:38:22 2018 | ||||
Map Report | Current | lun. 23. avr. 07:38:26 2018 | ||||
Place and Route Report | Current | lun. 23. avr. 07:38:31 2018 | ||||
Power Report | ||||||
Post-PAR Static Timing Report | Current | lun. 23. avr. 07:38:34 2018 | ||||
Bitgen Report | Current | lun. 23. avr. 07:38:39 2018 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | mar. 24. avr. 15:31:48 2018 | |
WebTalk Report | Current | lun. 23. avr. 09:07:47 2018 | |
WebTalk Log File | Current | lun. 23. avr. 09:07:48 2018 |