CmdMaCC Project Status (04/20/2018 - 16:26:56)
Project File: CmdMCC.xise Parser Errors: No Errors
Module Name: CmdMaCC Implementation State: Programming File Generated
Target Device: xc3s50a-5tq144
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 17 1,408 1%  
Number of 4 input LUTs 10 1,408 1%  
Number of occupied Slices 14 704 1%  
    Number of Slices containing only related logic 14 14 100%  
    Number of Slices containing unrelated logic 0 14 0%  
Total Number of 4 input LUTs 23 1,408 1%  
    Number used as logic 10      
    Number used as a route-thru 13      
Number of bonded IOBs 13 108 12%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.14      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentven. 20. avr. 16:19:32 2018   
Translation ReportCurrentven. 20. avr. 16:19:38 2018   
Map ReportCurrentven. 20. avr. 16:19:43 2018   
Place and Route ReportCurrentven. 20. avr. 16:19:50 2018   
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrentven. 20. avr. 16:19:54 2018   
Bitgen ReportCurrentven. 20. avr. 16:19:59 2018   
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Dateven. 20. avr. 16:02:43 2018
WebTalk ReportCurrentven. 20. avr. 16:26:55 2018
WebTalk Log FileCurrentven. 20. avr. 16:26:56 2018

Date Generated: 04/20/2018 - 16:26:56