Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (ISE) - P.20131013 Target Family: Spartan3A and Spartan3AN
OS Platform: NT64 Target Device: xc3s50an
Project ID (random number) dea62dcbdfcf4509a794fe82f10eb2a0.B65F32CFD237460BA56327FE47528301.35 Target Package: tqg144
Registration ID 174114161_177743590_210619533_100 Target Speed: -5
Date Generated 2018-06-17T10:17:28 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-3230M CPU @ 2.60GHz CPU Speed 2594 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=3
  • 8-bit comparator greater=3
Counters=6
  • 26-bit up counter=3
  • 8-bit up counter=3
Registers=6
  • Flip-Flops=6
MiscellaneousStatistics
  • AGG_BONDED_IO=17
  • AGG_IO=17
  • AGG_SLICE=42
  • NUM_4_INPUT_LUT=69
  • NUM_BONDED_IBUF=13
  • NUM_BONDED_IOB=4
  • NUM_BUFGMUX=1
  • NUM_CYMUX=63
  • NUM_LUT_RT=39
  • NUM_SLICEL=42
  • NUM_SLICE_FF=51
  • NUM_XOR=45
NetStatistics
  • NumNets_Active=112
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=30
  • NumNodesOfType_Active_CNTRLPIN=60
  • NumNodesOfType_Active_DOUBLE=125
  • NumNodesOfType_Active_DUMMY=94
  • NumNodesOfType_Active_DUMMYESC=13
  • NumNodesOfType_Active_GLOBAL=5
  • NumNodesOfType_Active_HFULLHEX=6
  • NumNodesOfType_Active_HLONG=2
  • NumNodesOfType_Active_HUNIHEX=11
  • NumNodesOfType_Active_INPUT=131
  • NumNodesOfType_Active_IOBOUTPUT=13
  • NumNodesOfType_Active_OMUX=84
  • NumNodesOfType_Active_OUTPUT=85
  • NumNodesOfType_Active_PREBXBY=28
  • NumNodesOfType_Active_VFULLHEX=8
  • NumNodesOfType_Active_VLONG=5
  • NumNodesOfType_Active_VUNIHEX=7
  • NumNodesOfType_Gnd_DOUBLE=2
  • NumNodesOfType_Gnd_INPUT=6
  • NumNodesOfType_Gnd_OMUX=3
  • NumNodesOfType_Gnd_OUTPUT=5
  • NumNodesOfType_Gnd_PREBXBY=8
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_INPUT=3
  • NumNodesOfType_Vcc_PREBXBY=3
  • NumNodesOfType_Vcc_VCCOUT=4
SiteStatistics
  • IBUF-DIFFMLR=2
  • IBUF-DIFFMTB=5
  • IBUF-DIFFSLR=2
  • IBUF-DIFFSTB=4
  • IOB-DIFFMLR=2
  • IOB-DIFFSLR=2
  • SLICEL-SLICEM=4
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=13
  • IBUF_DELAY_ADJ_BBOX=13
  • IBUF_INBUF=13
  • IBUF_PAD=13
  • IOB=4
  • IOB_OUTBUF=4
  • IOB_PAD=4
  • SLICEL=42
  • SLICEL_C1VDD=6
  • SLICEL_CYMUXF=33
  • SLICEL_CYMUXG=30
  • SLICEL_F=36
  • SLICEL_FFX=27
  • SLICEL_FFY=24
  • SLICEL_G=33
  • SLICEL_GNDF=15
  • SLICEL_GNDG=18
  • SLICEL_XORF=24
  • SLICEL_XORG=21
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:13]
  • IBUF_DELAY_VALUE=[DLY0:13]
  • IFD_DELAY_VALUE=[DLY0:13]
  • SEL_IN=[SEL_IN:13] [SEL_IN_INV:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS33:13]
  • PULL=[PULLUP:8]
IOB
  • O1=[O1_INV:0] [O1:4]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:4]
  • SUSPEND=[3STATE:4]
IOB_PAD
  • DRIVEATTRBOX=[12:4]
  • IOATTRBOX=[LVCMOS33:4]
  • SLEW=[SLOW:4]
SLICEL
  • BX=[BX_INV:3] [BX:9]
  • BY=[BY:3] [BY_INV:0]
  • CE=[CE:30] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:27]
  • CLK=[CLK:30] [CLK_INV:0]
  • SR=[SR:30] [SR_INV:0]
SLICEL_CYMUXF
  • 0=[0:33] [0_INV:0]
  • 1=[1_INV:0] [1:33]
SLICEL_CYMUXG
  • 0=[0:30] [0_INV:0]
SLICEL_FFX
  • CE=[CE:27] [CE_INV:0]
  • CK=[CK:27] [CK_INV:0]
  • D=[D:24] [D_INV:3]
  • FFX_INIT_ATTR=[INIT0:27]
  • FFX_SR_ATTR=[SRLOW:27]
  • LATCH_OR_FF=[FF:27]
  • SR=[SR:27] [SR_INV:0]
  • SYNC_ATTR=[SYNC:27]
SLICEL_FFY
  • CE=[CE:24] [CE_INV:0]
  • CK=[CK:24] [CK_INV:0]
  • D=[D:24] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:24]
  • FFY_SR_ATTR=[SRLOW:24]
  • LATCH_OR_FF=[FF:24]
  • SR=[SR:24] [SR_INV:0]
  • SYNC_ATTR=[SYNC:24]
SLICEL_XORF
  • 1=[1_INV:0] [1:24]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IBUF
  • I=13
  • PAD=13
IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=13
  • SEL_IN=13
IBUF_INBUF
  • IN=13
  • OUT=13
IBUF_PAD
  • PAD=13
IOB
  • O1=4
  • PAD=4
IOB_OUTBUF
  • IN=4
  • OUT=4
IOB_PAD
  • PAD=4
SLICEL
  • BX=12
  • BY=3
  • CE=30
  • CIN=27
  • CLK=30
  • COUT=30
  • F1=36
  • F2=12
  • G1=33
  • G2=12
  • SR=30
  • XQ=27
  • YQ=24
SLICEL_C1VDD
  • 1=6
SLICEL_CYMUXF
  • 0=33
  • 1=33
  • OUT=33
  • S0=33
SLICEL_CYMUXG
  • 0=30
  • 1=30
  • OUT=30
  • S0=30
SLICEL_F
  • A1=36
  • A2=12
  • D=36
SLICEL_FFX
  • CE=27
  • CK=27
  • D=27
  • Q=27
  • SR=27
SLICEL_FFY
  • CE=24
  • CK=24
  • D=24
  • Q=24
  • SR=24
SLICEL_G
  • A1=33
  • A2=12
  • D=33
SLICEL_GNDF
  • 0=15
SLICEL_GNDG
  • 0=18
SLICEL_XORF
  • 0=24
  • 1=24
  • O=24
SLICEL_XORG
  • 0=21
  • 1=21
  • O=21
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s50an-tqg144-5 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s50an-tqg144-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s50an-tqg144-5 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s50an-tqg144-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • xpwr -intstyle ise <fname>.ncd <fname>.pcf -o <fname>.pwr
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s50an-tqg144-5 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s50an-tqg144-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • ibiswriter -intstyle ise -truncate 20 <fname>.ncd <fname>.ibs
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s50an-tqg144-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s50an-tqg144-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s50an-tqg144-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s50an-tqg144-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s50an-tqg144-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
Start 0 0 0 0 0 0 0
_impact 3 1 0 0 0 0 0
bitgen 79 79 0 0 0 0 0
ibiswriter 1 1 0 0 0 0 0
map 79 79 0 0 0 0 0
ngdbuild 89 89 0 0 0 0 0
par 79 79 0 0 0 0 0
trce 79 79 0 0 0 0 0
xpwr 1 1 0 0 0 0 0
xst 162 162 0 0 0 0 0
 
Help Statistics
Search words with results
mhz ( 1 )
Help files
/doc/usenglish/isehelp/ise_c_imp_strategies.htm ( 1 ) /doc/usenglish/isehelp/ite_c_overview.htm ( 1 )
/doc/usenglish/isehelp/pim_c_introduction_efuse.htm ( 1 ) /doc/usenglish/isehelp/pim_c_introduction_indirect_programming.htm ( 1 )
/doc/usenglish/isehelp/pim_db_file_generation_preferences.htm ( 1 ) /doc/usenglish/isehelp/pim_db_programming_properties.htm ( 1 )
/doc/usenglish/isehelp/pim_r_examples.htm ( 1 ) /doc/usenglish/isehelp/pim_r_supported_spi_bpi_proms.htm ( 1 )
/doc/usenglish/isehelp/pn_c_setting_window_layout.htm ( 1 ) /doc/usenglish/isehelp/pn_db_adding_source_files.htm ( 1 )
/doc/usenglish/isehelp/pn_db_design_properties.htm ( 2 ) /doc/usenglish/isehelp/pn_db_nsw_select_ip.htm ( 1 )
/doc/usenglish/isehelp/pn_p_printing_a_file.htm ( 1 ) /doc/usenglish/isehelp/pp_db_configuration_options.htm ( 1 )
/doc/usenglish/isehelp/xpa_c_clock_name_async_signals.htm ( 1 ) /doc/usenglish/isehelp/xpa_c_frequency.htm ( 1 )
/doc/usenglish/wizards/arwz/awz_db_dcmcf.htm ( 1 ) http://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?topic=hardware+data+sheets ( 1 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_SelectedInstanceHierarchicalPath=/tb_CmdM3
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserBrowsedStrategyFiles=C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2018-04-20T14:29:12 PROP_intWbtProjectID=B65F32CFD237460BA56327FE47528301
PROP_intWbtProjectIteration=35 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_selectedSimRootSourceNode_behav=work.tb_CmdM3 PROP_xilxBitgCfg_GenOpt_EnableCRC=false
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=false
PROP_DevFamily=Spartan3A and Spartan3AN PROP_xilxBitgCfg_GenOpt_BinaryFile=true
PROP_DevDevice=xc3s50an PROP_DevFamilyPMName=spartan3a
PROP_DevPackage=tqg144 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-5 PROP_PreferredLanguage=VHDL
FILE_UCF=1 FILE_VHDL=6
 
Power Data
Customer
Customer=TBD Customer Class=TBD
Device
Family=Spartan3a Die=xc3s50an Package=tqg144 Speedgrade=-5
Tool Data
version=14.7 platform=win CPU=1 secs Peak Memory=267 MB
Tool=ise Num run=1
Power Settings
Temp grade=Commercial Process=Typical Settings file=No Simulation file=None
Simu_net_matched=NA Netlist_net_matched=NA PCF file=Yes Pct_clock_constrained=0
Pct_inputs_defined=0 User_junc_temp=0.0 Ambient temp=25.0 User effective thetaJA=NA
Airflow=0 heatsink=None User ThetaSA=NA Board selection=Medium (10x10)
Board layers=8 to 11 User ThetaJB=NA User Board Temp=NA Junction temp=25.6
Num run=1
Tool Defaults
Input toggle=12.5 Output toggle=12.5 Output enable=100.0 Bi-dir toggle=12.5
Bidir output enable=100.0 Output load=5.0 FF toggle=12.5 ram enable=50.0
ram write=50.0 DSP output toggle=12.5 Set/Reset probability=1.0 Set/Reset toggle=1.0
Enable probability=99.0 Enable toggle=1.0
Power Results
On-chip power=15.07 Effective ThetaJA=38.9 ThetaSA=0.0 ThetaJB=32.8
Off-chip power=-0.00
Thermal Power
Logic=0.00 Signal=0.00 Clock=2.24 BRAM=0.00
DSP=0.00 PLL=0.00 MMCM=0.00 PCIE=0.00
IO=0.00 GTX=0.00 DevStatic=12.82
Supply Power
Vccint voltage=1.20 Vccint total current=3.89 Vccint static current=2.02 Vccint dynamic current=1.87
Vccaux voltage=3.30 Vccaux total current=3.00 Vccaux static current=3.00 Vccaux dynamic current=0.00
Vcco25 voltage=2.50 Vcco25 total current=0.20 Vcco25 static current=0.20 Vcco25 dynamic current=0.00
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDRE=51 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=12
NGDBUILD_NUM_INV=9 NGDBUILD_NUM_LUT1=39 NGDBUILD_NUM_LUT2=24 NGDBUILD_NUM_MUXCY=63
NGDBUILD_NUM_OBUF=4 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=45
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDRE=51 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=12
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=9 NGDBUILD_NUM_LUT1=39 NGDBUILD_NUM_LUT2=24
NGDBUILD_NUM_MUXCY=63 NGDBUILD_NUM_OBUF=4 NGDBUILD_NUM_PULLUP=8 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=45
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s50an-5-tqg144 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=ieee
Fuse Resource Usage=577 ms, 33656 KB