CmdMaCC Project Status (04/20/2018 - 16:26:56) | |||
Project File: | CmdMCC.xise | Parser Errors: | No Errors |
Module Name: | CmdMaCC | Implementation State: | Programming File Generated |
Target Device: | xc3s50a-5tq144 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 17 | 1,408 | 1% | ||
Number of 4 input LUTs | 10 | 1,408 | 1% | ||
Number of occupied Slices | 14 | 704 | 1% | ||
Number of Slices containing only related logic | 14 | 14 | 100% | ||
Number of Slices containing unrelated logic | 0 | 14 | 0% | ||
Total Number of 4 input LUTs | 23 | 1,408 | 1% | ||
Number used as logic | 10 | ||||
Number used as a route-thru | 13 | ||||
Number of bonded IOBs | 13 | 108 | 12% | ||
Number of BUFGMUXs | 1 | 24 | 4% | ||
Average Fanout of Non-Clock Nets | 2.14 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | ven. 20. avr. 16:19:32 2018 | ||||
Translation Report | Current | ven. 20. avr. 16:19:38 2018 | ||||
Map Report | Current | ven. 20. avr. 16:19:43 2018 | ||||
Place and Route Report | Current | ven. 20. avr. 16:19:50 2018 | ||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | Current | ven. 20. avr. 16:19:54 2018 | ||||
Bitgen Report | Current | ven. 20. avr. 16:19:59 2018 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | ven. 20. avr. 16:02:43 2018 | |
WebTalk Report | Current | ven. 20. avr. 16:26:55 2018 | |
WebTalk Log File | Current | ven. 20. avr. 16:26:56 2018 |